(1) Field of the Invention
The present invention relates to a method of fabricating a CMOS(Complementary Metal-Oxide-Semiconductor) transistor of integrated circuits.
(2) Description of the Related Art
Integrated circuits which are based on complementary metal-oxide-semiconductor (CMOS) technologies are firmly established in modern electronics. A CMOS transistor, which comprises an n-channel(NMOS) and a p-channel(PMOS) transistor, provides the important characteristics needed for both low power dissipation and high integration density designs.
The conventional method of fabricating a CMOS needs five lithographic processes from defining gates to source/drain implantation. The process steps from defining gates to source/drain implantation are briefly described as follows:
(a). forming a first photo resist over a conducting layer and defining gates of both NMOS and PMOS regions. PA1 (b). forming a second photo resist over the NMOS (or PMOS) region and defining a first lightly doped region, and then executing a first ion implantation to form a lightly doped drain/source of an NMOS (or PMOS) transistor. PA1 (c). forming a third photo resist over the PMOS (or NMOS) region and defining a second lightly doped region, and then executing a second ion implantation to form a lightly doped drain/source of a PMOS (or NMOS) transistor. PA1 (d). forming sidewall spacers of the gates of the NMOS transistor and the PMOS transistor. PA1 (e). forming a fourth photo resist over the NMOS (or PMOS) region and defining a first source/drain region, and then executing a third ion implantation to form a drain/source of the NMOS (or PMOS) transistor. PA1 (f). forming a fifth photo resist over the PMOS (or NMOS) region and defining a second source/drain region, and then executing a third ion implantation to form a drain/source of the PMOS (or NMOS) transistor.
Every lithographic process includes lots of steps, such as dehydration bake, priming, photo resist coating, soft bake, exposure, development, after develop inspection and line width measurement, post bake and deep UV hardening, and so on. As mentioned above, the conventional method of fabricating a CMOS needs five lithographic processes from defining gates to source/drain implantation. Therefore, the conventional method takes a lot of cost and fabrication time, and thus decreases the throughput of the production.
The present invention discloses a new method of fabricating a CMOS by using only two lithographic processes. Accordingly, the present invention can not only reduce the cost and time of the manufacture, but also promote the process margin of fabricating the PMOS or the NMOS device of the CMOS.